Applications Engineer Physical Design/Fill - (Design Enablement)
at Intel
Phoenix, Arizona, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 22 Jul, 2024 | USD 185123 Annual | 28 Apr, 2024 | 1 year(s) or above | Intel,Computer Engineering,Addition,Density,Cadence Virtuoso | No | No |
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Description:
JOB DESCRIPTION
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborate on requirements with internal partners to define the scope, execution planning, and competitive solutions to meet the customer’s needs.
This position’s supporting role will drive solutions for ASIC tools/flows when customers use intel PDK collaterals in Physical design domain. You will also lead the collaboration across ourTD/DE/QnR organizations to find the best path to resolve the issue, along with owning/maintaining training documents, user guide, and customer ticket support.
As a DEAS (Design Enablement Application and Support) key member, you will use your communication skills to interact with customers directly while applying analytical problem-solving capability to identify the key requests, root-causing the issue, and teamwork with DE stakeholders to support and enable the customer’s success.
DesignEnablement
QUALIFICATIONS
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 4+ years of experience or MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering or a related field.
5+ years of experience in two or more of the following areas:
- Intel and/or external foundry process technology knowledge in advance nodes
- Exposure to layout, schematic entry using Cadence Virtuoso and Synopsys Custom Designer
- Development/support or handling of issues pertaining to DRC, LVS, antenna, density and fill on foundry process technology
- Exposure to one or more EDA tools on fill related issues (Synopsys ICV, Cadence Pegasus, Siemens Calibre)
Preferred Qualifications:
- Experience and background in analytical problem-solving to identify the key requests and root-causing the issue.
Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:1.0Max:5.0 year(s)
Electrical/Electronic Manufacturing
Engineering Design / R&D
Other
BSc
Electrical, Electrical Engineering, Engineering
Proficient
1
Phoenix, AZ, USA