ASIC Design Engineer - Memory Cache Controller

at  Apple

SUMMARY

Posted: May 9, 2024
Role Number:200550667
Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy

DESCRIPTION

Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis. Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team. Develop/debug RTL design of different sections of the cache. Work with physical design team to close timing of the same.

KEY QUALIFICATIONS

• Development of memory systems.
• Experience in RTL/micro-architecture definition.
• Experience in PPA (performance/power/area) analysis.
• Knowledge of dedication coherent memory system or interconnect architectures.
• Strong cache design background including good understanding of different memory organizations and tradeoffs.
• Knowledge of dedication memory subsystem and dram controller.
• Hands on Experience with multi-processor cache coherence protocols

EDUCATION & EXPERIENCE

Bachelors Degree + 0 Years of Experience.

ADDITIONAL REQUIREMENTS

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• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Please refer the Job description for details