ASIC Digital Design Engr, Sr Staff

at  Synopsys

JOB DESCRIPTION AND REQUIREMENTS

You will be part of the R&D in Solutions Group at our Munich Design Center in Germany. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Verification using latest Verification methodology Flows .
You will be part of the DesignWare IP Verification R&D team at Synopsys & be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. You will work closely with RTL designers and be part of a global team of expert Verification Engineers. You will be working on verifying the IP for the next generation Ethernet protocols for commercial, Enterprise and Automotive applications. The role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and analysis and meeting quality metric goals and regression management.

Key Qualifications & Experience

• Typically requires BS in EE with 5+ years of relevant experience or MS with 4+ years of relevant experience in the verification of IP cores and/or SOC RTL designs.
• Must have experience in developing HVL (System Verilog) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.
• Strong knowledge of building test bench components for UVM is a definite advantage
• Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
• Exposure to verification methodologies such as VMM/OVM/UVM/ is required.
• Working knowledge and experience of one or more of the connectivity protocols such as ETHERNET, PCIe, USB, DDR, eMMC, MIPI, Ethernet, AMBA is preferred. Prior Ethernet knowledge will be a definite plus.
• Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired.
• Exposure to IP design and verification processes including VIP development is an added advantage.
• There will be strong focus on functional coverage driven methodology. So the corresponding mindset is a must.
• Having experience with PCS – Phy simulation interop, bring up and verification is an added advantage.
• It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem solving skills and show high levels of initiative

Please refer the Job description for details