ASIC Digital Design Internship
at Synopsys
Markham, ON, Canada -
| Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
|---|---|---|---|---|---|---|---|
| Immediate | 07 Sep, 2024 | Not Specified | 08 Jun, 2024 | N/A | Perl,Systemverilog,Python,Languages,C | No | No |
Required Visa Status:
| Citizen | GC |
| US Citizen | Student Visa |
| H1B | CPT |
| OPT | H4 Spouse of H1B |
| GC Green Card |
Employment Type:
| Full Time | Part Time |
| Permanent | Independent - 1099 |
| Contract – W2 | C2H Independent |
| C2H W2 | Contract – Corp 2 Corp |
| Contract to Hire – Corp 2 Corp |
Description:
JOB DESCRIPTION AND REQUIREMENTS
Starting in 2024, this 16-month internship position will be with our Solutions Group in Mississauga or Markham, Canada.
Responsibilities:
- RTL coding, analog block modeling, and writing testbenches in SystemVerilog.
- Defining synthesis design constraints and resolving STA issues.
- Defining Clock/Reset domain crossing design constraints.
- Debugging RTL and gate-level simulation failures
REQUIREMENT SUMMARY
Min:N/AMax:5.0 year(s)
Information Technology/IT
Engineering Design / R&D
Information Technology
Graduate
Proficient
1
Markham, ON, Canada
