ASIC Digital Design

at  Synopsys

Calgary, AB, Canada -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate05 Sep, 2024Not Specified05 Jun, 20242 year(s) or aboveScripting Languages,Signal Design,Languages,Access,It,Rtl Design,Verilog,Artificial Intelligence,Object Oriented Programming,Disabilities,Models,PcieNoNo
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Description:

JOB DESCRIPTION AND REQUIREMENTS

Seeking a highly motivated and innovative digital engineer with excellent theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design and verification team, the candidate will be involved in digital design and verification of current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products. The position offers an excellent opportunity to work with a skilled team of DV engineers responsible for delivering high-end mixed-signal design. The activities would include:

  • Working with verification team on debugs/ and verifying the correctness of the RTL design.
  • Understanding the design.
  • Integrating analog schematics/behavior models with digital design.

Requirements:

  • BSEE with at least 2 years industry or direct related experience with the following:
  • Experience with UVM, verification methodologies and relevant verification experience would be a plus.
  • Familiarity with Verilog, SV/VHDl
  • Familiarity with digital simulation, waveform viewing tools
  • Prior digital design or Computer Engineering coursework
  • Experience with some scripting languages.
  • Exposure to object-oriented programming would be a plus
  • Experience writing scripts in languages such as Perl and Unix shell would be a plus.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

Responsibilities:

  • Working with verification team on debugs/ and verifying the correctness of the RTL design.
  • Understanding the design.
  • Integrating analog schematics/behavior models with digital design


REQUIREMENT SUMMARY

Min:2.0Max:7.0 year(s)

Information Technology/IT

Engineering Design / R&D

Information Technology

Graduate

Proficient

1

Calgary, AB, Canada