ASIC Synthesis Specialist

at  Nokia

The NOKIA Optics Subsystems group develops the front-ends for coherent optical long-distance transmission modules to interconnect network nodes and data centers. We are expanding and looking for highly motivated and experienced engineers to join us to develop the next generations of transmission systems.
Within Optics Subsystems, the SoC (System-on-Chip) team members architect, specify, design, verify and test the ASICs for the optical modules. Our main goal is to extend the optical reach and transmission bandwidth and at the same time reduce the power and floorspace needs by using the latest chip technologies.
Sounds interesting?
Be sure to check out details about our latest development, the Photonic Service Engine 6s ASIC\SoC:
https://www.nokia.com/networks/optical-networks/pse-6s/
As ASIC engineer involved in the architecture and development of sub-micron devices, your tasks are highly demanding in technical and soft skills. You will be working in a culture of autonomy and individual responsibility as part of an international development team, in charge of building system-on-chip devices for coherent transmission systems.

As ASIC Synthesis Specialist your tasks will consist of:

• Lead and drive the ASIC synthesis process, collaborating closely with the design and verification teams.
• Develop and optimize synthesis scripts, methodologies, and tool chain to enhance efficiency and performance.
• Implement RTL (Register Transfer Level) to gate-level netlist synthesis using industry-standard tools.
• Collaborate with physical design teams to ensure successful handoff of synthesized designs.
• Troubleshoot and resolve synthesis-related issues to meet project timelines.
• Mentor and provide technical guidance to junior team members.
• Stay current with industry trends and advancements in ASIC synthesis methodologies.
• Investigate and optimize power consumption by leveraging on latest CMOS technology nodes and applying dedicated power analysis tools and techniques.
• Select available intellectual properties to be integrated into our design as well as communication with third party IP suppliers.
• Collaborate with systems engineering, hardware, software and firmware development teams and test engineering in international Nokia locations.
• Strong knowledge and practical experience about ASIC synthesis process and methodologies as well as overall back-end flow with (usage of Synopsys toolchain and) related EDA tools
• Knowledge and practical experience about ASIC design and verification, respective implementation tools (Synopsys, Siemens/Mentor, Cadence ), the related design languages (VHDL, Verilog, System Verilog), script programming (TCL, Python) and overall development environment
• Proven experience in Formal Verification of design results (e.g. LEC, CDC, PDV) as well as use of hardware emulators
• Good communication skills, fluent written and spoken English (required), with a strong interest to collaborate with international partners.

It would be beneficial if you also had:

• Inter-disciplinary and inter-cultural collaboration experience
• Knowledge in LINUX-based systems IT infrastructure management
• Knowledge in ASIC verification methodologies (e.g. UVM)

• Some knowledge about optical transmission standards like OIF, IEEE, ITU-T etc.Knowledge about coherent optical transmission systems and their functional components, with special attention to their optimal implementation.

• The position requires a Master’s degree or PhD in Electronic Engineering, Microelectronics, Telecommunication Engineering or similar.

• Lead and drive the ASIC synthesis process, collaborating closely with the design and verification teams.
• Develop and optimize synthesis scripts, methodologies, and tool chain to enhance efficiency and performance.
• Implement RTL (Register Transfer Level) to gate-level netlist synthesis using industry-standard tools.
• Collaborate with physical design teams to ensure successful handoff of synthesized designs.
• Troubleshoot and resolve synthesis-related issues to meet project timelines.
• Mentor and provide technical guidance to junior team members.
• Stay current with industry trends and advancements in ASIC synthesis methodologies.
• Investigate and optimize power consumption by leveraging on latest CMOS technology nodes and applying dedicated power analysis tools and techniques.
• Select available intellectual properties to be integrated into our design as well as communication with third party IP suppliers.
• Collaborate with systems engineering, hardware, software and firmware development teams and test engineering in international Nokia locations.
• Strong knowledge and practical experience about ASIC synthesis process and methodologies as well as overall back-end flow with (usage of Synopsys toolchain and) related EDA tools
• Knowledge and practical experience about ASIC design and verification, respective implementation tools (Synopsys, Siemens/Mentor, Cadence ), the related design languages (VHDL, Verilog, System Verilog), script programming (TCL, Python) and overall development environment
• Proven experience in Formal Verification of design results (e.g. LEC, CDC, PDV) as well as use of hardware emulators
• Good communication skills, fluent written and spoken English (required), with a strong interest to collaborate with international partners