Compiler Engineer

at  Untether AI

PLEASE NOTE: WHILE OUR ENGINEERING HQ IS IN TORONTO, THIS IS A REMOTE OPPORTUNITY AND WE WELCOME APPLICANTS FROM ANYWHERE IN NORTH AMERICA.

Untether AI is building the world’s highest performance pure-digital AI inference startup. We’re a rapidly growing Toronto-based startup, with employees across Canada and the US, building next generation hardware AI accelerators for neural net inference. We are investing in software in a big way in order to make it as seamless as possible for researchers and developers to successfully deploy neural networks on our hardware.
We’re looking for best in class engineers to join our existing top-notch team. When you join Untether AI, you will be part of a team that designs, develops and verifies the software that interacts with our chip, collaborating with our hardware engineers and with fellow software engineers in the process. By creating software that fully realizes the capabilities of the hardware, you will help get AI inference to the general populace.
As part of this exceptional team, you are able to - and get excited by - identifying functional/performance bottlenecks and how to alleviate them in order to achieve scalable and reliable software. You excel in an environment with complex software and hardware designs.
We are looking for an experienced Compiler Engineer. Our Compiler Engineers write software that translates a wide variety of neural nets into efficient mappings and fast implementations on our accelerator hardware, from data-in to data-out.

PREFERRED SKILLS & EXPERIENCE

• Computer Science, Engineering or related degree, preferably MS or PhD
• 2+ years of related experience
• Thorough understanding of deep neural nets
• Experience developing the internals of modern optimizing compilers
• Understanding of advanced optimization techniques

• Build software that maps a neural net onto our hardware
• Devise and implement multiple data layout strategies
• Build a tool that will solve a network layout for a set of constraints within the hardware given the available strategies
• Implement efficient mappings between data layouts
• Evaluate current and proposed hardware architecture for future products
• Work closely with algorithm design and architecture teams