Copy of Principal Verification Engineer
at Renesas Electronics
Praha, Praha, Czech -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 24 Jun, 2024 | Not Specified | 26 Mar, 2024 | 5 year(s) or above | Multi Cultural Environment,Communication Skills,Electronics,Systemverilog,Systemc,Assertion Based Verification,Computer Engineering,Computer Science,Continuous Improvement,Formal Verification | No | No |
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Description:
Company Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
Job Description
KNOWLEDGE, SKILLS AND EXPERIENCE:
Technical
- The ideal candidate has an experience of 5-10 years in advanced verification methodologies, owning the verification of complex digital and mixed signal designs
- SystemVerilog for verification using advanced verification methodologies (preferably OVM/UVM or similar such as Specman-e, SystemC, etc.)
- Assertion based verification and Formal verification
- Expert in constrained random verification and metric driven verification
- Expert in simulation and regressions tools e.g. Cadence Incisive, vManager, IMC
- Familiar with either Verilog or VHDL RTL coding and ASIC design methodology
- Familiar with behavioral modelling of analog blocks
General:
- Concise and proactive communication skills within a multi-site and multi-cultural environment
- Ability to persuade and influence others based on technical facts
- Takes responsibility for solutions and makes them happen, self-motivated
- Looks for continuous improvement in own and Dialog work practices
Qualifications
QUALIFICATIONS:
Degree in electrical engineering, electronics, computer engineering, computer science, or equivalent
How To Apply:
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Responsibilities:
JOB PURPOSE:
The purpose of this job is to guarantee specification compliance of digital or mixed signal design by means of advanced verification methodologies and concepts. It involves definition, deployment and improvement of state-of-the-art verification methodologies.
PRINCIPAL ACCOUNTABILITIES:
- Verification planning, maintenance, feature extraction, verification test case and checker development
- Develop efficient, reusable state-of-the-art verification environments and testbench structures
- Develop verification strategy for digital and mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM
- Initiate and participate in review meetings with design and verification engineers
- Lead digital verification of mixed signal ICs or sub-systems
- Work closely with the Analog Mixed Signal (AMS) verification and analog design team
- Mentor junior engineers in the team
REQUIREMENT SUMMARY
Min:5.0Max:10.0 year(s)
Electrical/Electronic Manufacturing
Engineering Design / R&D
Other
Graduate
Computer Science, Electrical, Electrical Engineering, Engineering
Proficient
1
Praha, Czech