Deep Learning Compiler Engineer for Ryzen AI NPU
at Advanced Micro Devices Inc
San Jose, CA 95124, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 09 Sep, 2024 | Not Specified | 10 Jun, 2024 | N/A | Python,C++,Computer Science,Diffusion,Design Principles | No | No |
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Description:
QUALIFICATIONS:
- Master’s degree or PhD. in Computer Science, Engineering, or a related field (or Bachelor’s degree with significant experience).
- Strong understanding of the dataflow scheduling and memory hierarchy in a multi-core processor architecture.
- Knowledge of compiler design principles (front-end, middle-end, back-end).
- Experience with machine learning frameworks (e.g., TensorFlow, PyTorch).
- Experience working with ML compilers (e.g., MLIR, TVM).
- Experience with ML models such as CNN, LSTM, LLMs, Diffusion is a must.
- Excellent programming skills in Python, C++, or similar languages.
- Experience with machine learning hardware architectures (e.g., GPUs, TPUs, VLIW) is a plus.
- A passion for innovation and a strong desire to push the boundaries of machine learning performance.
Responsibilities:
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:
We are looking for a talented Deep Learning Compiler SW Engineer to join our growing team in the AI group and play a crucial role in developing SW suite to deploy cutting-edge ML models on AMD’s XDNA Neural Processing Unit (NPU). You will be responsible for designing, implementing, and optimizing compilers, that translate Gen-AI ML inference models like SDXL-Turbo, Llama2, Mistral, etc into low-level code for specialized DL inference accelerator. Your work will directly impact the efficiency, scalability, and reliability of our Deep learning applications. If you thrive in a fast-paced environment and love working on cutting edge ML inference models, this role is for you.
RESPONSIBILITIES:
- Design and develop novel algorithms for tiling and mapping quantized ML workloads on Ryzen AI NPU.
- Analyze and transform intermediate representations of ML models (computational graphs) for efficient execution.
- Collaborate with architects and runtime software engineers to understand performance requirements of different operators and translate them into effective compiler strategies.
- Collaborate with kernel developers to understand kernel tiling requirements and strategize the dataflow and L1/L2 buffer allocation schemes.
- Develop back-end optimization passes to convert high-level representation into driver calls.
- Implement compiler optimizations for performance, resource usage, and compute efficiency.
- Develop and maintain unit tests and integration tests for the compiler to support different generations of NPU architecture.
- Enable detailed profiling and debugging tools for analyzing performance bottlenecks and deadlocks in dataflow schemes.
- Stay up-to-date on the latest advancements in ML compiler technology and hardware architectures.
REQUIREMENT SUMMARY
Min:N/AMax:5.0 year(s)
Computer Software/Engineering
IT Software - Application Programming / Maintenance
Software Engineering
Graduate
Computer Science, Engineering
Proficient
1
San Jose, CA 95124, USA