Design-for-Test (DFT) Implementation Engineer - DFT Solutions Team

at  Intel

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

• Candidate must possess a BS in Electrical or Computer Engineering and 6+ yrs. exp. OR MS in Electrical or Computer Engineering and 4+ yrs. experience in:
• SoC Design-For-Test (DFT) principles such as SCAN for logic testing, BIST and repair for memory test, Boundary SCAN,
• Test insertion, test pattern generation, and verification.
• Industry-standard DFT tools such as Siemens Tessent DFT, Synopsys DFT Compiler, DFTMax, TetraMax.

How to Stand out (Preferred Qualifications):

• Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience.
• Experience with the DFT integration of IP (e.g. DDR, SerDes, PLL’s) into an SoC.
• Experience with IEEE1149 JTAG Boundary SCAN, IEEE1687 IJTAG
• Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug.
• Programming skills; experience writing routines for data manipulation using advanced data structures; languages include PERL, Tcl/Tk.
• DFT architecture development and planning for an SoC.

• Development of the SoC Test Implementation plan to individualize the standardized DFT solutions to the SoC, including the hierarchical test architecture and the strategies to address SoC-specific DFT requirements.
• Definition of the standardized DFT flow steps, deployment of the tool infrastructure and flow automation to implement the SoC DFT in a highly repeatable and predictable fashion.
• Insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for High-Volume Manufacturing (HVM) testing of the design.
• Development of the Static Timing Analysis (STA) constraints for physical construction and timing closure in all DFT modes, and collaboration with the Physical Design team to achieve timing closure for the DFT modes.
• Collaborating with the HVM Test Engineering team during silicon bring-up and New Product Introduction (NPI).
• Scaling the standardized DFT solutions to the wider XNE DFT Team across the products of the XNE portfolio