Design Verification Engineer

at  Apple

Cupertino, California, USA -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate23 Sep, 2024USD 300200 Annual24 Jun, 202410 year(s) or abovePython,Scripting Languages,Automation,Tcl,Affirmative Action,Disabilities,Ips,Working Experience,Apple,PerlNoNo
Add to Wishlist Apply All Jobs
Required Visa Status:
CitizenGC
US CitizenStudent Visa
H1BCPT
OPTH4 Spouse of H1B
GC Green Card
Employment Type:
Full TimePart Time
PermanentIndependent - 1099
Contract – W2C2H Independent
C2H W2Contract – Corp 2 Corp
Contract to Hire – Corp 2 Corp

Description:

SUMMARY

Posted: Jan 13, 2023
Role Number:200451263
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Do your life’s best work here at Apple! This role is for a design verification engineer who will enable bug-free first silicon for the IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

DESCRIPTION

In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are expected to: Lead and develop detailed test and coverage plans based on the micro-architecture. Drive verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment and work closely with analog team to ensure overall bug-free IP design.

KEY QUALIFICATIONS

  • Extensive knowledge of SystemVerilog test-bench language and UVM
  • Experience developing scalable and portable test-benches
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations
  • Some working experience with different DDR protocols including Low power version
  • Should have been in technical lead position
  • Experience with IP verification methodology for IPs such as PHYs, PLLs etc.
  • Working knowledge of one of the scripting languages: Python, Perl, TCL

EDUCATION & EXPERIENCE

BS degree in technical discipline with minimum 10 years of relevant experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

Responsibilities:

Please refer the Job description for details


REQUIREMENT SUMMARY

Min:10.0Max:15.0 year(s)

Information Technology/IT

IT Software - Other

Information Technology

BSc

Proficient

1

Cupertino, CA, USA