ESD CAD Engineer

at  Intel

JOB DESCRIPTION

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. The PERC ESD development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. AS part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel’s most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a BS degree with 1+ years of experience or master’s degree in Electrical Engineering or Computer Engineering or related field.
1+ years of experience in the following:
Experience with Calibre or ICV or Pegasus PERC tools.
ESD/Latch-up Pre-Si models
Preferred Qualifications:
1+ years of experience in the following:
(HBM and CDM), I/O design and methodologies.
Debugging skills.
Experience in writing physical verification runsets.
Experience in extraction and physical design domain.
Experience in scripting languages for QA automation.
Experience in driving cross functional and industry wide initiatives and taskforces.
Knowledge of semiconductor device physics, process technology, and design rules.

Please refer the Job description for details