Foundry Services - Structural Design (Physical Design) Engineer - Lead

at  Intel

Austin, TX 78746, USA -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate13 Aug, 2024USD 259425 Annual14 May, 20243 year(s) or aboveScripting,Dfx,Design Techniques,Physical Design,The Foundry,Formal Verification,Addition,Computer Science,Tcl,VizNoNo
Add to Wishlist Apply All Jobs
Required Visa Status:
CitizenGC
US CitizenStudent Visa
H1BCPT
OPTH4 Spouse of H1B
GC Green Card
Employment Type:
Full TimePart Time
PermanentIndependent - 1099
Contract – W2C2H Independent
C2H W2Contract – Corp 2 Corp
Contract to Hire – Corp 2 Corp

Description:

WHAT WE NEED TO SEE (MINIMUM QUALIFICATIONS):

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

The candidate must have a Bachelor’s degree in Computer/Electrical Engineering or Computer Science and 8+ years of experience -OR- a Master’s Degree in Computer/Electrical Engineering or Computer Science and 6+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science and 3+ year of experience with the following:

  • Experience with owning the full chip level and taping out multiple complex SoCs
  • Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc.
  • Hands on experience with Full-Chip and partition level physical design (APR digital logic).
  • RTL to gds2 flow and basic device physics.
  • Scripting with tcl, perl, shell etc. to solve the basic design problem.
  • Internal flow development and understand nuances of Physical Design (Structural Design) flow.
  • Experience with 7nm technology or below.

HOW TO STAND OUT (PREFERRED QUALIFICATIONS):

  • Experience with handling PDKs (Process Design Kit).
  • Strong Experience with Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.
  • Strong proficiency in PERL, tcl, and/or shell scripting.
  • Good handle on Tape-out interaction with the foundry and worked on Post-Silicon activities.
  • Exposure to various industry standard Physical Design and Sign-Off closure tools.
  • Understanding of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc.

Responsibilities:

  • Developing and supporting digital circuit design with cell libraries. Performing digital circuit design and simulation.
  • Designing, developing, modifying, and evaluating digital electronic parts, components or integrated circuitry for use in digital electronic equipment and other hardware systems.
  • Determines design approaches and parameters. Performs digital circuit design, verification and layout, data path design and digital block synthesis, place and route, sign-off through tape-out


REQUIREMENT SUMMARY

Min:3.0Max:8.0 year(s)

Electrical/Electronic Manufacturing

Engineering Design / R&D

Other

Graduate

Computer/electrical engineering or computer science and 3 year of experience with the following

Proficient

1

Austin, TX 78746, USA