FPGA Design Verification Engineer (bonus eligible)

at  General Dynamics Mission Systems Inc

Basic Qualifications :
Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master’s degree plus a minimum of 6 years of relevant experience.
CLEARANCE REQUIREMENTS: Ability to obtain a Department of Defense Top Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities for this Position:

Sign on Bonus up to $3000 for New Hires.
As a Cyber FPGA Design Verification engineer, you’ll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products.
We encourage you to apply if you have any of these preferred skills or experiences: Experience with OVM / UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting languages; VHDL or similar hardware description languages.