Junior Analog Designer

at  ZEROERROR SYSTEMS PTE LTD

Singapore, Southeast, Singapore -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate12 Jun, 2024USD 9000 Monthly12 Mar, 20243 year(s) or abovePower Management,Spectre,Cadence,Matlab,Ldo,Cmos,Bicmos,Circuit AnalysisNoNo
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Description:

COMPANY OVERVIEW

Zero-Error Systems (ZES) provides high-reliability semiconductor integrated circuits (ICs)/electronic modules and reliability testing services that enable higher functionality, lower cost, longer lifetime and higher power efficiency for space, and various power management applications.

KEY REQUIREMENTS

  • Bachelor’s or Masters in electrical engineering or a related field
  • Strong experience in analog IC design, particularly bandgap, amplifier, comparator, low-dropout regulator (LDO), current sensing, power switch, etc
  • Proficiency with industry-standard tools such as Cadence, Spectre, HSPICE, and Matlab.
  • Familiarity with CMOS, BiCMOS, and other process technologies
  • Excellent problem-solving skills and the ability to work in a fast-paced startup environment.
  • At least 3 years of experience in analog IC design with 2 IC product tapeouts
  • Some understanding of circuit analysis and implementation
  • Strong expertise in power management, including DC/DC converter design
  • Able to perform design verifications
  • Is a good team player
  • Excellent communication skillsAble to think critically and is results oriented
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Responsibilities:

ABOUT THE ROLE

ZES is currently seeking a junior analog designer to join our team and help us revolutionise the industry. The analog designer will collaborate with other IC designers to work on different analog IC designs for various applications including commercial, automotive and space.

KEY RESPONSIBILITIES

  • Fast development of analog IC physical designs, including layout drawing, design rule checks (DRCs), Layout Versus Schematic (LVS)
  • Layout extractions and analysis for IC designers
  • Develop analog and/or digital library cells in various technologies (e.g. Complementary Metal-Oxide-Semiconductor (CMOS) & Silicon-On-Insulator (SOI))
  • Layout digital cells for various trade-offs (including speed, power, area, reliability)
  • Layout analog circuits and input and output (I/O) circuits
  • Characterize digital cell cells for timing and power analyses
  • Construct test structures for validating various digital and analog cells
  • Layout integration and optimization
  • Advise IC designers for best layout practice
  • Work with the IC design team to deliver IC physical designs
  • Support the team lead for layout design integrationsAny other duties assigned
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REQUIREMENT SUMMARY

Min:3.0Max:8.0 year(s)

Electrical/Electronic Manufacturing

Engineering Design / R&D

Other

Graduate

Proficient

1

Singapore, Singapore