Logic Design Engineer

at  Intel

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

WHAT WE NEED TO SEE (MINIMUM QUALIFICATIONS):

Bachelors in Electrical/Computer Engineering and 6+ years of experience -OR- Master’s degree in Electrical/Computer Engineering with 4+ years of industry experience in:

• Experience reading and interpreting technical specs to come up with Microarchitecture and implement RTL design in System Verilog.
• Computer system architecture and Digital Design knowledge.
• OVM/UVM methodology to interact with the Validation designers for Val content development.

HOW TO STAND OUT (PREFERRED QUALIFICATIONS):

• Experience with working in mixed-signal design like SerDes or PLLs.
• Experience with automated Place-and-route (APR) team to convey constraints and work together to close timing issues.
• Scripting in at least one of the following interpreted language (e.g. TCL, Perl, Python, Ruby).
  Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

• Logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Participating in the definition of architecture and microarchitecture features of the block being designed.
• Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Supporting SoC customers to ensure high quality integration and verification of the IP block.
• Driving quality assurance compliance for smooth IP SoC handoff