Logic/RTL Design Engineer

at  Intel

JOB DESCRIPTION

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Follows secure development practices to address the security threat model and security objects within the design.
• Works with IP providers to integrate and validate IPs at the SoC level.
• Drives quality assurance compliance for smooth IPSoC handoff.

QUALIFICATIONS

• You must possess the below minimum qualifications to be initially considered for this position.

• Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

• Bachelors degree in Electrical/Computer Engineering or related field and 4+ years of experience Or a Masters degree in Electrical/Computer Engineering or related field and 3+ years of experience.
• 4+ years of RTL coding and/or IP integration experience using Verilog/SystemVerilog.
• 2+ years prior experience in addressing LINT, CDC and Static Timing Analysis issues.
• 2+ years prior experience with Power UPF.
• 1+ years prior experience as IP design engineer or SOC integration engineer interfacing with IP design teams.
• 1+ year prior experience in SOC micro-architecture (clocking, reset, power, etc) in terms block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.

How to Stand out (Preferred Qualifications):

• 8+ years of RTL coding and/or IP integration experience.
• 3+ years experience with common interfaces like DDR, PCIe, UCIe, HBM or other designs.
• Good integration knowledge of analog circuits and mixed signal designs.
• Implement RTL in SystemVerilog, perform unit level testing, debug tests, SDC and UPF generation.
• Integrate hard IP and soft IPs including industry standard and proprietary interfaces.
• Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking and support Static Timing Analysis.
• Ensure designs are delivered on time and with the highest quality by using proper checks.
• Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members.
• Work with verification team for test plan/strategy to meet all functional requirements and performance.
• Work with timing and physical team for timing closure and meet power and area goals.
• Support project managers with effort estimations and resource planning.
• Support team leader in coaching, training and development team members.
• Knowledge of Synthesis/Auto P and R, Primetime, post-silicon testing, etc. are a plus.

Please refer the Job description for details