Manager, Mask Design

at  Renesas Electronics

Company Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
Job Description
This position is in Power Attached Products and Solutions (PAS) group. The purpose of this position is to create cell and top-level layouts for our automotive PMIC and DCDC design teams. The devices include power management, analog products and digital core layouts. The candidate will utilize the Cadence tool set and requires interaction with circuit designers, layout designers, and CAD team.

QUALIFICATIONS

• 8 years minimum required, 15 years experience preferred.
• 5 years project lead, supervisor or management experience.
• Basic understanding of electronic principles dealing with circuit and layout design
• Good working knowledge of BCD and CMOS processes
• Familiar with IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout physical verification
• Familiar with device physics is preferred
• Team player with good communication skills
• BS in Electrical Engineering or related engineering field or Technical Degree
• Power FET and R3D experience preferred
  Additional Information
  Renesas Electronics Corporation empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com.
  Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.
  Renesas Electroncs is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law

• Manage and lead a remote/overseas team of layout designers
• Work closely with group to track progress and create goals
• Top-level layout floor planning
• Custom cell layout and verification
• Work with circuit designers to build physical design floor-plan, create package bond diagrams
• Complete the physical layout design with the constraints of circuit design requirements
• Execute mask data release and archiving
• Verify the physical layout design to meet both circuit design requirements and process requirements
• Use new tools and methods to improve layout design quality and efficiency