JOB DESCRIPTION

As a Memory Design Graduate Trainee, you will be part of Intel Design Enablement (DE) focused on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.

As a member of this team, your responsibilities include (but not limited to):

• Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO)
• Product/design enablement
• Memory bitcell and complex periphery IC layout and automation
• Memory array/IP design, memory circuit innovation, testchip design/execution/validation
• Pre/post-Si validation/debug to enable yield and parametric tracking/ramp

QUALIFICATIONS

Minimum Qualifications:

• You should have Bachelor/Master/PhD in Electrical Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field.
• Proficient in TCL, Perl or Python programming language.
• Unix/Linux operating system

Preferred Qualifications:

• Ability to work in a fast-paced, collaborative, and often intense project schedule.
• Excellent communication and interpersonal skills, a good team-player as well as able to work independently.
• Creative mind and self-motivated.
• Analytical problem solving and multitasking.
• Able to do pathfinding or research independently to find solutions.

designenablement

• Memory pathfinding activities and power performance area (PPA) optimization through design technology co-optimization (DTCO)
• Product/design enablement
• Memory bitcell and complex periphery IC layout and automation
• Memory array/IP design, memory circuit innovation, testchip design/execution/validation
• Pre/post-Si validation/debug to enable yield and parametric tracking/ram