Mixed-Signal Cosim Engineer

at  Synopsys

COSIM ENGINEER

Seeking a motivated and innovative mixed signal AMS co-simulation verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3/4 SERDES products. The position offers an excellent opportunity to work with an expert team of digital, analog and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Main responsibilities include:

• Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment.
• Analyzing/verifying the functionalities of SERDES.
• Defining and tracking verification testplans.
• Debugging simulation failures in both analog and digital domains.
• Creating top level analog testbenches for SERDES.
• Performing physic layout reliability analysis for SERDES.

Key Requirements:

• Bachelor in Electrical Engineering or any other relevant degree.
• Script Writing in languages such as Perl, Python and Unix shell.
• Familiar with Verilog and SystemVerilog.
• Experience or knowledge with analog circuitry such as bandgap, opamp, PLL, Transmitter/Receiver designs.

The Solutions Group high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys’ extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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• Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment.
• Analyzing/verifying the functionalities of SERDES.
• Defining and tracking verification testplans.
• Debugging simulation failures in both analog and digital domains.
• Creating top level analog testbenches for SERDES.
• Performing physic layout reliability analysis for SERDES