Pre-Si Emulation SV Engineer

at  Intel

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:

Bachelor degree in Electrical Engineering, Computer Engineering, or similar discipline and 1+ years’ experience OR Master’s degree in Electrical Engineering, Computer Engineering, or similar discipline.

• Knowledge of Computer System Architecture and/or related software-hardware sub-systems.
• Proficiency in various hardware Debugging Tools, methodologies using Pre-Silicon Emulator and Post Silicon Boards for issues in the hardware-software boundaries.
• Experience with Firmware/Embedded Firmware/Software development or verification.
• Experience with software programming in Python, C and/or C++ language.

Preferred Qualifications:

• Hands-on experience at Emulation/Silicon/FPGA debug, or RTL validation is a plus.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products.
This is an entry level position and will be compensated accordingly.