Principal Design Verification Engineer

at  Microsoft

The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.
We are looking for a Principal Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

REQUIRED/MINIMUM QUALIFICATIONS

• 9+ years of related technical engineering experience
• OR Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
• OR Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 8+ years of industry experience in design verification with a proven track record of delivering complex Application-Specific Integrated Circuit or System on Chip.
• 5+ experience in leading technical team with Verifying complex interconnect, Fabric/Network On Chip or Networking Application-Specific Integrated Circuit.

OTHER QUALIFICATIONS:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

ADDITIONAL OR PREFERRED QUALIFICATIONS

• 15+ years of industry experience in design verification with a proven track record of delivering complex CPU or SoC IPs.
• Demonstrated expertise in one or more of the following: interconnect fabrics, NOCs, AXI-4 protocol base other complex IP/blocks or subsystems.
• Experience with IP/SOC verification for a full product cycle from definition to silicon, including writing IP/block or subsystem level architecting DV environment, estimating efforts, test plans, developing tests, debugging failures and coverage signoff.
• Experience of working on AI/Machine Learning (ML)SoCs
• In depth knowledge of verification and debug principles, testbenches, Universal Verification Methodology (UVM) or C based test environments.
• Experience in post-silicon bring-up of complex SoCs involving complex NOC.
• Working knowledge of writing assertions, coverage and / or formal verification.
• Knowledge of industry standard bus interfaces such as Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocols.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
• Scripting languages such as Zsh, Bash, Python or Perl.
• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams within Microsoft and with external vendors.
  Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.
  Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
  Microsoft will accept applications for the role until April 25, 2024.
  Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations

• Establish yourself as an integral member of a design verification team for the development of AI components with focus on verifying functions and features.
• Lead a pre-silicon verification team for the development of custom Intellectual Property (IP) and Subsystem (SS) components with focus on architectural and micro-architectural based functions and features.
• Collaborate with the architecture and design teams to ensure the implementation meets both architectural and micro-architectural intent.
• Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
• Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
• Provide technical leadership through mentorship and teamwork.