Principal Engineer -Memory Technology/Design Lead

at  Intel

QUALIFICATIONS

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related discipline
• 10+ years of professional experience.

Required Experience/Knowledge:

• Knowledge of the CMOS ASIC design flow.
• Custom digital circuit design, simulation, layout design, and verification
• Knowledge of EDA tools used for analog, digital and mixed-signal circuit design.
• Post-Si validation experienc

Preferred Experience/Knowledge:

• Design, characterization, and verification of custom memory circuits such as SRAM, Register Files, ROM, DRAM, MRAM, etc.
• Design trade-offs between power, performance, and area (PPA)
• Design technology co-optimization (DTCO

As the Memory Technology/Design Lead, you will partner with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel’s advanced CMOS process technologies.

Responsibilities:

• Memory pathfinding activities and power, performance, area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
• Memory bit-cell and complex periphery IC layout and automation.
• Memory array/IP design, memory circuit innovation, test-chip design.
• Pre-Si verification, post-Si validation, and debugging to enable yield and parametric tracking/ramp.
• Internal and external customer engagement to enable optimized usage of Intel memory technology

Required Experience/Knowledge:

• Knowledge of the CMOS ASIC design flow.
• Custom digital circuit design, simulation, layout design, and verification
• Knowledge of EDA tools used for analog, digital and mixed-signal circuit design.
• Post-Si validation experience

Preferred Experience/Knowledge:

• Design, characterization, and verification of custom memory circuits such as SRAM, Register Files, ROM, DRAM, MRAM, etc.
• Design trade-offs between power, performance, and area (PPA)
• Design technology co-optimization (DTCO)