JOB DESCRIPTION

The Group: Intel’s Advanced Design (AD) team resides within the Design Enablement (DE) organization, which collaborates closely with our partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD is to guide process technology definition, and design prototypes in Intel’s latest process technology, supporting Intel’s internal and external design customers.
The future of Moore’s Law: 3D-IC
https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html
https://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/
https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu
The Role: The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key 3D-IC strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System

Your responsibilities may include, but not be limited to:

• Design analysis and optimization for 3D-IC Advanced Silicon and Packaging technology definition and certification.
• Innovate on 3D-IC Heterogenous integration as a holistic co-optimization from System to Silicon in partnership with domain experts, extending DTCO to STCO (System Technology Co-Optimization).
• Establish 3D-IC prototypes across market segments.
• Collaboration with Product teams to identify critical product characteristics and target setting requirements.
• Engage with EDA providers on pathfinding of 3D-IC EDA feature requirements and 3D-IC design methodology development.
• Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation
• 3D-IC Test Chips validation of 3D-IC technology platforms and design methodology

DesignEnablement

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a MS degree with 10+ years of experience or PhD degree with 8+ years of experience in Electrical Engineering or Computer Engineering and or related field.

Direct experience in the following areas:

• Expert on establishing Static Timing Analysis (STA) methodology and signoff including variation analysis.
• Experience developing digital design flows and EDA vendor engagement.
• Experience establishing prototypes, reference/Testchip designs and/or Product designs.
• Multiple clock domain and Low Power Design.
• Scripting skills using a programming language such as Python, TCL, etc.

Preferred Qualifications:

Experience in the following:

• Intel/External Foundry experience.
• Physical Design Methodologies for optimal Performance Power Area Cost (PPAC) in advanced technologies.
• Experience with ARM-based system PPA optimization
• Semiconductor devices and 3D Packaging technologies.
• Reference designs and TFM for STCO/3D-IC.
• Circuit design, Standard Cell Library and Memory Architectures.
• Power Management Design Methodology and Power Distribution Network (PDN), IR/EM, Thermals.

• Design analysis and optimization for 3D-IC Advanced Silicon and Packaging technology definition and certification.
• Innovate on 3D-IC Heterogenous integration as a holistic co-optimization from System to Silicon in partnership with domain experts, extending DTCO to STCO (System Technology Co-Optimization).
• Establish 3D-IC prototypes across market segments.
• Collaboration with Product teams to identify critical product characteristics and target setting requirements.
• Engage with EDA providers on pathfinding of 3D-IC EDA feature requirements and 3D-IC design methodology development.
• Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation
• 3D-IC Test Chips validation of 3D-IC technology platforms and design methodolog