Senior E/E & Semiconductor Engineer - Design Verification Engineer

at  Capgemini

LIFE AT CAPGEMINI

Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:

• Collaborating with teams of creative, fun, and driven colleagues
• Flexible work options enabling time and location-based flexibility
• Company-provided home office equipment
• Virtual collaboration and productivity tools to enable hybrid teams
• Comprehensive benefits program (Health, Welfare, Retirement and Paid time off)
• Other perks and wellness benefits like discount programs, and gym/studio access.
• Paid Parental Leave and coaching, baby welcome gift, and family care/illness days
• Back-up childcare/elder care, childcare discounts, and subsidized virtual tutoring
• Tuition assistance and weekly hot skill development opportunities
• Experiential, high-impact learning series events
• Access to mental health resources and mindfulness programs
• Access to join Capgemini Employee Resource Groups around communities of interest

CAPGEMINI IS AN EQUAL OPPORTUNITY EMPLOYER ENCOURAGING DIVERSITY IN THE WORKPLACE. ALL QUALIFIED APPLICANTS WILL RECEIVE CONSIDERATION FOR EMPLOYMENT WITHOUT REGARD TO RACE, NATIONAL ORIGIN, GENDER IDENTITY/EXPRESSION, AGE, RELIGION, DISABILITY, SEXUAL ORIENTATION, GENETICS, VETERAN STATUS, MARITAL STATUS OR ANY OTHER CHARACTERISTIC PROTECTED BY LAW.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.
Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
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Applicants for employment in Canada must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in Canada by Capgemini

JOB DESCRIPTION:

We are looking for Senior Design Verification Engineer

REQUIRED SKILLS

• 10 years of experience in UVM based verification
• UVM/SystemVerilog/C/C++/Python

NICE TO HAVE SKILLS:

• GLS verification knowledge
• Low power – UPF – verification
• ARM based SoC level verification experience
  Job Developer
  Schedule Full-time
  Primary Location CA-ON-Toronto
  Organization ERD PPL CA

• Proficient in System Verilog assertions and verification using UVM experience
• Familiarity with C/C++ model integration in verification environments
• Debug skills at IP and subsystem level