Senior Machine Learning Engineer for Chip Design and Verification

at  Synopsys

The Senior Machine Learning Engineer will collaborate closely with hardware engineers, data scientists, product managers, and notably, core developers of Electronic Design Automation (EDA) tools. The role is focused on developing, deploying, and maintaining machine learning models aimed at enhancing the efficiency, reliability, and speed of chip design and verification processes through seamless EDA tool integration.

QUALIFICATIONS

• PhD in Computer Science, Electrical Engineering, Machine Learning, or a related field.
• 2+ years of experience in machine learning with a focus on generative techniques and optimization problems.
• Proficiency in Python and machine learning frameworks like TensorFlow or PyTorch.
• Solid understanding of EDA tools for chip design and verification such as Cadence, Synopsys, or Mentor Graphics, and experience collaborating with their core developers.
• Experience with cloud computing services like AWS, GCP, or Azure.
• Strong understanding of algorithmic complexity, data structures, and software design.
• Excellent communication skills, both written and verbal.

• Develop Generative AI and Machine Learning systems for Solution Generation & Optimization in RTL Design, RTL and System Verification, and Power/Performance/Area Optimization
• Develop Large Language Model fine-tuning flows, Prompt Engineering, and Prompt fine-tuning
• Work in close collaboration with core EDA tool developers to understand domain-specific needs and tailor machine learning solutions for seamless integration.
• Preprocess and analyze large datasets of chip simulations, tests, and performance metrics.
• Implement machine learning pipelines for automated data collection, feature extraction, training, and inference in the EDA environment.
• Evaluate the performance of machine learning models, and optimize them for computational efficiency, scalability, and integration with EDA tools.
• Develop visualization tools to interpret the results of machine learning models.
• Maintain clear and detailed documentation of models, pipelines, and experiments.
• Keep abreast of emerging technologies in machine learning and chip design to ensure our solutions remain state-of-the-art.