Senior Staff ASIC Physical Design Engineer

at  SUNLUNE SINGAPORE PTE LTD

Singapore, Southeast, Singapore -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate09 Jul, 2024USD 40000 Monthly11 Apr, 20243 year(s) or aboveCommunication Skills,Primetime,Power Optimization,Static Timing Analysis,Network Design,Tcl,Physical Design,PerlNoNo
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Description:

QUALIFICATIONS

  • Degree or related field required
  • 3+ years industry experience required
  • Experience on high performance and low-power physical design
  • Experience on deep sub-micron process technology (14nm and below) taped outs
  • Experience on floor planning, power network design, power optimization/analysis, clock-tree design, static-timing analysis, DRC, LVS
  • Excellent interpersonal and communication skills
  • Experience on using Perl, TCL, Make, and other script languages
  • Experience on Synopsys or Cadence tools (Design Compiler, IC Compiler, StarRCXT, Primetime, Innovus)
  • Experience on Mentor or Synopsys verification tools (Calibre, ICV)

Responsibilities:

  • Advanced low-power physical design/integration flow development
  • Synthesis, floor planning and place & route
  • Full-chip floor planning and layout
  • Power network design and analysis
  • Support signoff timing closure, power integrity, and signal integrity
  • Physical Verification using DRC, LVS

REQUIREMENT SUMMARY

Min:3.0Max:8.0 year(s)

Information Technology/IT

Engineering Design / R&D

Information Technology

Graduate

Proficient

1

Singapore, Singapore