Server Power Integrity Engineer
at Advanced Micro Devices Inc
Santa Clara, CA 95054, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 11 Aug, 2024 | Not Specified | 12 May, 2024 | 8 year(s) or above | Power Delivery | No | No |
Required Visa Status:
Citizen | GC |
US Citizen | Student Visa |
H1B | CPT |
OPT | H4 Spouse of H1B |
GC Green Card |
Employment Type:
Full Time | Part Time |
Permanent | Independent - 1099 |
Contract – W2 | C2H Independent |
C2H W2 | Contract – Corp 2 Corp |
Contract to Hire – Corp 2 Corp |
Description:
An in-depth knowledge of the following is required:
- Transmission line theory and microwave engineering concepts such as S-parameter, impedance, SSN, etc.
- System-level timing analysis considering effects from silicon IO, package, and board.
- State-of-the-art PCB stack up/construction.
- In-depth knowledge of AC/DC power delivery, power integrity analysis.
- Expertise in modeling with Sigrity PowerDC and PowerSI
Responsibilities:
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:
ROLE:
AMD has an opening for Power Integrity engineer in Server Division working on platform power delivery network design and customer support for EPYC products.
KEY RESPONSIBILITIES:
An in-depth knowledge of the following is required:
- Transmission line theory and microwave engineering concepts such as S-parameter, impedance, SSN, etc.
- System-level timing analysis considering effects from silicon IO, package, and board.
- State-of-the-art PCB stack up/construction.
- In-depth knowledge of AC/DC power delivery, power integrity analysis.
- Expertise in modeling with Sigrity PowerDC and PowerSI.
REQUIREMENT SUMMARY
Min:8.0Max:13.0 year(s)
Information Technology/IT
Engineering Design / R&D
Software Engineering
Graduate
Proficient
1
Santa Clara, CA 95054, USA