Silicon Digital Design Engineer

at  Fresh Consulting

Fresh Consulting is a design-led, software development and hardware engineering company, offering end-to-end digital services to help companies innovate. We bring together amazing UX designers, sophisticated developers, digital strategists, and top-notch engineers to help companies create fresh experiences that connect humans, systems, and machines. We’ve been growing fast and need someone to help us continue managing high-quality work delivery in a fast-paced environment.
See more at freshconsulting.com Visit freshconsulting.com/portfolio to see our project work across several industries.
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Title: Silicon Digital Design Engineer
Duration: 1 year with possible extension
Location: Remote. Must live and work in AZ or CA or IL or IN or NV or NY or OR or TX or UT or WA
Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan and much more!
Hours: Minimum 40 Hours/Week

Role:

• Own ASIC IP RTL implementation for IP blocks.
• Ensure RTL written meets quality checks like Lint/CDC/RDC.
• Collaborate closely with design team members, technical leads, and the architecture team to ensure the block meets the power and performance requirements.
• Collaborate closely with the verification team to develop test plans and review test coverage.
• Perform IP integration.
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis.

Skills:

• 4+ years of experience as a Digital Design Engineer.
• Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC.
• Experience having worked on a design from scratch – code from the ground up (outline/provide project work, if available)
• Experience in RTL coding and coding for low power in ASICs.
• Experience in digital design µArchitecture.
• Familiarity with Verilog and SystemVerilog coding.
• Perl, Tcl, and Python (or similar) scripting experience

Education: BS in Electrical Engineering/Computer Science/Computer Engineering or equivalent experience

• Own ASIC IP RTL implementation for IP blocks.
• Ensure RTL written meets quality checks like Lint/CDC/RDC.
• Collaborate closely with design team members, technical leads, and the architecture team to ensure the block meets the power and performance requirements.
• Collaborate closely with the verification team to develop test plans and review test coverage.
• Perform IP integration.
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis