Silicon Verification Engineer (contract)
at Microsoft
Mountain View, CA 94043, USA -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 25 May, 2024 | USD 79 Hourly | 29 Feb, 2024 | 7 year(s) or above | Computer Science,C++,Static Timing Analysis,Computer Engineering,C | No | No |
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Description:
SILICON VERIFICATION ENGINEER (CONTRACT)
Please note that this is a contract role providing services to Microsoft through external staffing partners of Allegis Global Solutions. If you are selected for this role, you will be employed by AGS and will not be an employee of Microsoft.
SUMMARY:
The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.
REQUIREMENTS:
- 7-10 years of relevant experience required.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required.
- System Verilog and C/C++ coding a must.
- Chip/full system level ASIC Verification skills, and debug skills a must.
- Debug using waveforms a must, Verdi source level debug a plus.
- System level knowledge a must.
- System is defined as a test bench containing {CPU + multi-media engines } with hardware based coherency.
- System could be a simulation test bench, emulation test bench or a board.
- System level knowledge/verification does not mean signal integrity checking, electrical checks, EMC checks, thermal checks, ATPG testing on a board, DFT/DFx testing, static timing analysis, lint checking.
- Tests will be written in C/C++, compiled for CPU and will be run on simulation/emulation/board unchanged.
- Block/unit level verification skills using UVM knowledge desirable (not required for the work, but having this knowledge means the candidate has been working on verification in the recent past).
Responsibilities:
- Define, document, and implement a UVM verification environment including agents and scoreboards.
- Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
- Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
- Support post-silicon verification activities of the products working with design and product teams.
REQUIREMENT SUMMARY
Min:7.0Max:10.0 year(s)
Information Technology/IT
IT Software - QA & Testing
Software Engineering
Graduate
Electrical engineering computer engineering computer science or related degree required
Proficient
1
Mountain View, CA 94043, USA