SoC DFT Engineer

at  Advanced Micro Devices Inc

PREFERRED EXPERIENCE:

• Scan and ATPG, SSN, In-System ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic is a plus
• Knowledge of Verilog, C/C++ and scripting languages; experience with Perl and TCL is a plus
• Familiar with entire ASIC design flow, hands on working experience on ASIC DFT design and verification is an advantage
• Knowledge of UVM and OVM verification methodologies is an advantage
• Strong analytical/problem solving skills and pronounced attention to details.
• Experience in complex ASIC design (multi-million gates) and in DFT/DFD techniques such as JTAG/IEEE standards.
• Experience in verification of multiple PHY protocols such as PCIE, XGMI, WAFL, GDDR6, USB2/3.1 and Display port is a plus

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

As a SoC DFT Engineer, you’ll be a part of SOC (System-On-Chip) DFX team you will be involved in design, integration, Scan Insertion, ATPG, verification & timing analysis for state-of-the-art design-for-test and design-for-debug features in complex AMD products. You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification and emulation of those features until deliveries to PEO (product engineering organization) and debug on ATE (automated test equipment)

KEY RESPONSIBILITIES:

The successful candidate will report to the SOC DFT (Design-For-Test) Scan and ATPG Manager and will have the following responsibilities:

• End to End block-level Scan insertion and ATPG
• Assist in the testing and validation of ATPG strategies to ensure high Test coverage and quality
• Perform gate-level verification and validation of block-level ATPG patterns
• Analyze test results and provide feedback for optimization and improvement
• Collaborate with cross-functional teams to integrate block-level scan and ATPG solutions into overall product designs
• Perform scan pattern retargeting of block level ATPG patterns
• Develop RTL and integrate internal/external RTL logic into SoC (System-On-Chip)
• Write and review verification test-plans
• Develop verification infrastructure, test-bench components and test-cases
• Drive performance verification on all DFT structures
• Generate and verify DFT structural patterns and functional patterns
• Participate in ATE bring-up and debug the DFT patterns on ATE and platform