JOB DESCRIPTION

The Group:
Intel’s Advanced Design (AD) team resides within the Design Enablement (DE) organization, which collaborates closely with our partners in process technology, IP, and products spanning client/server and networking products. The primary focus of AD is to guide process technology definition, and design prototypes in Intel’s latest process technology, supporting Intel’s internal and external design customers.
The future of Moore’s Law:
3D-IC
https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html
https://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/
https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu
The Role:
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System

Your responsibilities may include, but not be limited to:

• Innovate on 3D-IC Heterogenous integration as a holistic co-optimization from System to Silicon in partnership with domain experts, extending DTCO to STCO (System Technology Co-Optimization).
• Micro-architecture definition to establish 3D-IC prototypes across market segments. Collaboration with Product teams to identify critical product characteristics and target setting requirements.
• IP configuration, RTL coding, Verilog system simulation, pre and post silicon validation and system simulation.

The candidate should also exhibit the following behavioral traits and/or skills:

• Analytical, problem-solving skills and out of the box thinking. Verbal/written communication skills.

DesignEnablement

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must possess a MS degree with 10+ years of experience or PhD degree with 6+ years of experience in Electrical Engineering or Computer Engineering or related field.

Experience in the following:

• Micro-architecture trade-offs and Logic design.
• Microarchitecture of global SoC flows such as reset, clocking, power management .
• Pre-silicon and post-silicon validation. Experience in Silicon power-on.

Preferred qualifications:

• Test program development and/or execution.
• ASIC validation methodology, Verilog testbenches, UVM.
• Design for Test (DFT) and Design for Debug (DFD), ATPG, MBIST, etc.
• Architecture trade-offs and Design Methodologies for optimal Performance Power Area Cost (PPAC) in advanced technologies.
• Experience with ARM-based Systems.

• Innovate on 3D-IC Heterogenous integration as a holistic co-optimization from System to Silicon in partnership with domain experts, extending DTCO to STCO (System Technology Co-Optimization).
• Micro-architecture definition to establish 3D-IC prototypes across market segments. Collaboration with Product teams to identify critical product characteristics and target setting requirements.
• IP configuration, RTL coding, Verilog system simulation, pre and post silicon validation and system simulation