SoC Logic Design Engineer

at  Intel

WHO WE ARE:

Intel Federal LLC is a wholly owned subsidiary of Intel Corporation responsible for managing Intel’s business with the US Federal Government. We collaborate with Sales and Marketing, government affairs, and Intel business units (BUs) across Intel to develop and execute programs for US Government (USG) agencies. Intel Federal works with and across the defense industrial base (DIB) and systems integrator (SI) ecosystem to deliver mission solutions to USG customers.

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information.

• Bachelor’s degree in electrical engineering or computer engineering and 1+ years of experience or
• Master’s Degree in Electrical Engineering or Computer Engineering and 6+ months of experience or a
• PhD in Electrical Engineering or Computer Engineering and related experience.

Must have the required degree or expect the required degree by July 2024.

• 1+ years of experience with Micro-architecture definition and RTL development
• 1+ years of experience with processors, accelerators, networking or IO integration
• 1+ years of experience with Computer Architecture, Microprocessor or Chip-set design methods

PREFERRED QUALIFICATIONS:

• Background in X86 or RISCV ISA and pipeline architecture/design
• Synopsys DC for synthesis and timing analysis
• Experience with SystemC and SystemVerilog

• Working with architects to define, implement the handshake logic between IP and SOC and integrate them.
• Working with architects and design engineers to generate micro-architecture and/or verification plan.
• Define Microarchitecture Specification (MAS) and develop RTL for logical blocks.
• Collaborate with design verification team to develop a detailed verification test-plan and support simulation bring-up, debug and bug fixes.
• Debug, fix, and validate pre- and post-silicon sub-system logic issues and bugs.
• Opportunities to also contribute to architecture definition and performance modeling