Sr. Principal Engineer - MLA Verification (AI2293)
at SiMa Technologies
San Jose, CA 95110, USA -
| Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
|---|---|---|---|---|---|---|---|
| Immediate | 27 May, 2024 | USD 305000 Annual | 01 Mar, 2024 | 15 year(s) or above | Good communication skills | No | No |
Required Visa Status:
| Citizen | GC |
| US Citizen | Student Visa |
| H1B | CPT |
| OPT | H4 Spouse of H1B |
| GC Green Card |
Employment Type:
| Full Time | Part Time |
| Permanent | Independent - 1099 |
| Contract – W2 | C2H Independent |
| C2H W2 | Contract – Corp 2 Corp |
| Contract to Hire – Corp 2 Corp |
Description:
JOB DESCRIPTION:
The MLA Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and computer vision pipeline at block, sub-system and SoC level. Will also be involved in bringup and debug on emulator.
JOB DESCRIPTION
As the MLA Design Verification Engineer, you will
- Participate in MLA architecture, micro-architecture and feature discussions and reviews
- Define and develop MLA test bench components using UVM & SystemVerilog
- Develop DV reference models as needed in C or SystemVerilog
- Develop and execute a test plan
- Verification execution of MLA and MLSoC functionality and performance measurements
- Lead Code coverage reviews and closure. SystemVerilog Assertion functional coverage development and closure
- Manage debug test and regression failures, as well emulation failures
- Work closely with the Architecture, MLSoC Hardware and MLA Software teams
How To Apply:
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Responsibilities:
Please refer the Job description for details
REQUIREMENT SUMMARY
Min:15.0Max:20.0 year(s)
Information Technology/IT
IT Software - System Programming
Software Engineering
Graduate
Proficient
1
San Jose, CA 95110, USA
