ADVANCING THE WORLD’S TECHNOLOGY TOGETHER

Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

WHAT YOU BRING

• Bachelors in Electrical/Computer Engineer with 10 years of relevant industry experience, or Masters in Electrical/Computer Engineer with 8 years or PhD in Electrical/Computer Engineer with 4 years in processor and SOC development or related field preferred.
• Experience in designing internal bus structure of the latest ARM bus or Tilelink.
• Well understand micro-architecture of cache coherent bus structure.
• Well understand RISC-V core or ARM core architecture.
• Strong background in microarchitecture and computer architecture.
• Experienced with hardware languages like Verilog, SystemVerilog, SystemC.
• Experience in micro architecture of SoC, interface sub systems, logic modules.
• Experience in architectural modeling & analysis.
• Good knowledge in ASIC design flow.
• Excellent communication and interpersonal skills.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.
  

  LI-SF1

The APL (Advanced Processor Lab) is one of research team of SAIT (Samsung Advanced Institute of Technology) which is Samsung’s R&D hub, established as the incubator for cutting-edge technologies. SAIT’s mission has covered various research areas from AI applications/algorithms research, neuromorphic processor, domain-specific accelerators to new materials, quantum computing, and super computer system.
APL is committed to shaping the future of CPU processor and SoC architecture for the most demanding applications of the future like AI and HPC. We are building the foundation of processors and the related platform which are applied to various business targets of Samsung in the future. For more practical and sustainable architecture, we emphasize that the CPU - programming core should be the center of technology to run all of heterogenous computing engines with complex software under easy-to-use programming environment. It requires innovative ways how to couple tightly with hardware engines as well as maximizing the efficiency and performance of CPU processor. And, beyond one-unit core architecture, the efficient and flexible inter-operation among multiple CPU cores for better scalability is essentially a key mission of the project. Therefore, we’re making a new architecture from the internal CPU core, attached accelerator and to SoC architecture.
Our team collaborates closely with other research groups in SAIT like applications, system modeling, network and physical implementation team. We also have several collaborations with innovative academic professors and researchers in the US. We have several successful experiences for commercialized accelerators and SoC for AI, and we continuously keep research and development for emerging technologies as well as realization to the products.
Location: Hybrid, working onsite at our office 3 days per week, with the flexibility to work remotely the remainder of your time

Job ID: 42051

• Develop a network-on-chip architecture for multi CPU cores.
• Design and develop cache-coherent bus for high-performance CPU cores.
• Design and research interconnection architecture for heterogeneous processors.
• Design and develop microarchitecture for multiple RISC-V CPUs and Tile-link based interfaces.
• Design micro-architecture and RTL, taking charge of synthesis, logic, and timing verification.
• Optimize the micro-architecture for the power/area efficiency.
• Collaborate with cross-functional teams and experts, including applications/software engineers, performance team, backend designers, and other architecture teams.
• Provide technical leadership and mentorship to hardware and software engineers.
• Complete other responsibilities as assigned.