Staff Memory Layout Engineer

at  MEDIATEK SINGAPORE PTE LTD

Our layout department is currently seeking result-driven candidates who can thrive in a fast-paced working environment and have a strong desire to make an impact within the organization. This position will be based in Singapore.

• Possess advanced level of understanding of memory architecture, and memory leaf cell layout creation.
• Posses good understanding of basic CMOS and finfet circuits;
• Experience and familiarity in various physical verification checks like DRC, LVS, ERC, Antenna, Density, ESD, LUP, EM, IR, etc.;
• Understanding and working knowledge of good layout practices (matching, etc), especially in advanced process nodes, like 7nm, 5nm, 3nm, 2nm etc, is preferred;
• Good understanding of deep sub-micron and DFM issues in layout design (WPE, LOD effects, etc.).
• Responsible for the development of memory layouts in advance CMOS and finfet processes;
• Perform physical verifications of different memory types, from bottom cells to top hierarchy;
• Undertake the assignments independently or in a team;
• Work closely with memory design engineers and memory compiler engineers to ensure highest quality memory layouts.