JOB DESCRIPTION

The Production Libraries Group is looking for a full-time member to work in standard cell library design and validation using Intel latest process technology for use by Intel CPU, Atom, Graphics, mixed signal IPs, Client, Sever, Chipset projects and IFS Foundry customers.
Candidate will be part of the Production Libraries team responsible for standard cells validation enablement doing EDA tools execution, validation automation development and maintenance, and design issues resolution.

Responsibilities include, but are not limited to:

• Perform ASIC design flow enablement, execution, PPA (Power, Performance, Area) analysis, synthesis, APR, and layout verification.
• Publish library PPA and trend analysis reports.
• Execute standard cell library collateral validation through industry and internal tools.
• Design and validate collateral rules associated with standard cell library collateral.
• Design and develop automation to ensure high quality of standard cell library models utilizing a combination of internal and industry design tools.
• Debug, root cause, and drive alignment and improvements in standard cell modeling.

Candidate must exhibit the following behavioral traits/skills:

• Possesses written and verbal communication skills.
• Customer/result orientation and the ability to work with external and internal.
• Engineering acumen and analytical skills.
• Customer oriented and able to work in a dynamic environment.
• Collaboration skills across geographically distributed teams and being willing to handle ambiguity while developing expertise in new areas and delivering quantifiable results will be key to the success in this role.
• Debugging skills.

DesignEnablement

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Candidate must have a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electronics Engineering or Hardware Engineering, Electrical and/or Computer Science/Engineering or related fields.

3+ years of experience in one or more of the following:

• Standard Cell Library design and development.
• Digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
• VLSI Design Automation (Physical Design Automation, Simulation, Timing Analysis, Reliability Analysis).
• Abstract models (ndm, lef) modeling expertise and usage with ICC2 and Innovus.

Preferred Qualifications:

3 + years of experience in the following:

• Experience with Industry standard ASIC tools .
• Library Compiler, Primetime, ICC2, Genus, Tempus, ICV, Fusion Compiler, TCL, Python.
• Experience in digital circuit design, front end model creation and functional verification.
• Digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
• Understanding of device physics.
• Experience with standard cell library characterization, Front End, Back End models generation, and validation.
• Experience working with EDA vendors to drive new features and capabilities.
• Knowledge of industry-standard EDA tools for VLSI circuit and layout design.
• Experience working in the Linux environment and its development tools.
• Standard cell level PPA modeling, simulation, and ROI analysis.
• Experience in CMOS power modeling and cell level optimization.
• CMOS and standard cell level device variation and Aging analysis.
• Familiarity working with EDA vendors and internal stakeholders.

• Perform ASIC design flow enablement, execution, PPA (Power, Performance, Area) analysis, synthesis, APR, and layout verification.
• Publish library PPA and trend analysis reports.
• Execute standard cell library collateral validation through industry and internal tools.
• Design and validate collateral rules associated with standard cell library collateral.
• Design and develop automation to ensure high quality of standard cell library models utilizing a combination of internal and industry design tools.
• Debug, root cause, and drive alignment and improvements in standard cell modeling