Standard Cell Library Design Engineer
at Broadcom
Yishun, Northwest, Singapore -
Start Date | Expiry Date | Salary | Posted On | Experience | Skills | Telecommute | Sponsor Visa |
---|---|---|---|---|---|---|---|
Immediate | 22 Jul, 2024 | Not Specified | 28 Apr, 2024 | 5 year(s) or above | Tcl,Teams,Physical Design,Virtuoso,Unix,Perl,Verilog,Python,Communication Skills,Scripting,Pnr,Syntax | No | No |
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Description:
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Job Description:
Broadcom’s Central Engineering Group builds the Foundation IP that powers Broadcom’s leading silicon product families.
In this position, the successful candidate will be part of the team responsible for the design, development and delivery of standard cell library foundation IP .
Job Responsibilities
- Design standard or custom digital logic and sequential cells or macros at the transistor level
- Simulate and analyze circuit designs using industry standard simulation tools
- Generate and verify library EDA models
- Run regression and other quality checks on library deliverables
- Interface with design teams to support their requirements
Key Requirements
- Digital or mixed-signal circuit design knowledge
- Understanding of cell layout or physical design
- Understanding of verilog, lef , .lib and other industry standard EDA models
- Familiarity with EDA tools used in STA and PnR
- Experience with .lib syntax including NLDM/CCS/LVF is a plus
- Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL or Python is strongly desired
Qualifications & Experience
Bachelor’s in Electrical or Computer Engineering and 5+ years of related experience required
Additional Qualifications
- Excellent written and verbal communication skills
- Collaborate and work within and across teams
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence
Responsibilities:
- Design standard or custom digital logic and sequential cells or macros at the transistor level
- Simulate and analyze circuit designs using industry standard simulation tools
- Generate and verify library EDA models
- Run regression and other quality checks on library deliverables
- Interface with design teams to support their requirement
REQUIREMENT SUMMARY
Min:5.0Max:10.0 year(s)
Electrical/Electronic Manufacturing
Engineering Design / R&D
Other
Graduate
Proficient
1
Yishun, Singapore